{"id":1301,"date":"2026-06-29T03:31:06","date_gmt":"2026-06-29T03:31:06","guid":{"rendered":"https:\/\/www.nvixeon.com\/stm32h745-dual-core-guide-running-cortex-m7-and-cortex-m4-simultaneously\/"},"modified":"2026-07-13T01:40:02","modified_gmt":"2026-07-13T01:40:02","slug":"stm32h745-dual-core-guide-running-cortex-m7-and-cortex-m4-simultaneously","status":"publish","type":"post","link":"https:\/\/www.nvixeon.com\/fr\/stm32h745-dual-core-guide-running-cortex-m7-and-cortex-m4-simultaneously\/","title":{"rendered":"STM32H745 Dual-Core Guide: Running Cortex-M7 and Cortex-M4 Simultaneously"},"content":{"rendered":"

The STM32H745 is one of the most capable microcontrollers STMicroelectronics has ever produced. It contains two independent processor cores \u2014 a Cortex-M7 running at up to 480MHz and a Cortex-M4 running at up to 240MHz \u2014 and both can execute code at the same time. This is not a marketing feature. It is a genuinely useful architectural capability that changes how you design embedded systems.<\/p>\n

In this guide we cover exactly how the dual-core system works, how to set it up in STM32CubeIDE, how the two cores communicate, and when you should actually use both cores versus sticking with just the M7.<\/p>\n

This guide applies directly to the NVX-H7 Compact<\/strong> and NVX-H7 Pro<\/strong> boards from Nvixeon, both of which are built around the STM32H745.<\/p>\n

\n

Understanding the STM32H745 Architecture<\/h2>\n

Two Cores, One Chip<\/h3>\n

The STM32H745 uses an Asymmetric Multi-Processing (AMP) architecture. Unlike symmetric multi-processing where cores run the same OS and share a task scheduler, AMP means each core runs its own independent firmware. The M7 runs one program. The M4 runs a completely different program. They share peripherals and memory but operate independently.<\/p>\n

    \n
  • \nCortex-M7:<\/strong> up to 480MHz, 1MB ITCM, 128KB DTCM, FPU, DSP, 6-stage pipeline with branch prediction\n<\/li>\n
  • \nCortex-M4:<\/strong> up to 240MHz, FPU, DSP, access to most peripherals\n<\/li>\n
  • \nShared SRAM:<\/strong> 512KB SRAM1 + 512KB SRAM2 accessible to both cores\n<\/li>\n
  • \nHardware semaphores (HSEM):<\/strong> 32 hardware semaphores for inter-core synchronisation\n<\/li>\n<\/ul>\n
    \n

    Which Core Boots First?<\/h3>\n

    The Cortex-M7 is the boot master. It starts first and is responsible for initialising the system, setting up clocks, and then releasing the Cortex-M4 from its hold state. The M4 cannot start executing until the M7 explicitly allows it.<\/p>\n

    \n

    Setting Up a Dual-Core Project in STM32CubeIDE<\/h2>\n

    Step 1 \u2014 Create a New Project<\/h3>\n

    Open STM32CubeIDE and create a new project. When the target selector appears, search for STM32H745 and select the correct variant for your board. When CubeMX asks which core to configure, select Cortex-M7 first.<\/p>\n

    \n

    Step 2 \u2014 Configure Clocks on the M7 Side<\/h3>\n

    All clock configuration must be done on the M7. In the Clock Configuration tab, set the system clock to 480MHz using PLL1. Set the M4 clock to 240MHz using PLL2.<\/p>\n

    \n

    Step 3 \u2014 Assign Peripherals to Cores<\/h3>\n

    In STM32CubeMX, each peripheral has a core assignment. The general rule:<\/p>\n

      \n
    • \nAssign high-bandwidth peripherals (Ethernet, USB HS, display) to the M7\n<\/li>\n
    • \nAssign real-time peripherals (PWM timers, CAN, UART) to the M4\n<\/li>\n
    • \nMark shared resources as shared and protect access with HSEM\n<\/li>\n<\/ul>\n
      \n

      Step 4 \u2014 Release the M4 from M7 Firmware<\/h3>\n

      In your M7 main.c, after completing system initialisation, release the M4:<\/p>\n

      __HAL_RCC_HSEM_CLK_ENABLE();
      HAL_HSEM_FastTake(HSEM_ID_0);
      HAL_HSEM_Release(HSEM_ID_0, 0);<\/code><\/pre>\n
      \n
      Inter-Core Communication Using HSEM<\/h2>\n
      The STM32H745 includes 32 hardware semaphores. These are atomic lock mechanisms that prevent both cores from accessing the same resource simultaneously.<\/p>\n
       \/\/ M7 \u2014 write shared data
      HAL_HSEM_FastTake(0);
      shared_buffer[0] = sensor_value;
      HAL_HSEM_Release(0, 0);

      \/\/ M4 \u2014 read shared data
      while (HAL_HSEM_FastTake(0) != HAL_OK) {}
      uint32_t value = shared_buffer[0];
      HAL_HSEM_Release(0, 0);<\/code><\/pre>\n
      \n
      Practical Use Cases<\/h2>\n
      Ethernet Gateway with Real-Time Motor Control<\/h3>\n
        \n
      • \nM7:<\/strong> lwIP TCP\/IP stack, MQTT, web dashboard\n<\/li>\n
      • \nM4:<\/strong> FOC motor control loop at 20kHz, encoder reading, PID controller\n<\/li>\n
      • \nShared:<\/strong> motor setpoint and telemetry via HSEM-protected shared SRAM\n<\/li>\n<\/ul>\n
        \n
        Display HMI with CAN Bus Logging<\/h3>\n
          \n
        • \nM7:<\/strong> LTDC display driver, touch input, UI rendering\n<\/li>\n
        • \nM4:<\/strong> FDCAN receive\/transmit, message parsing, alarm detection\n<\/li>\n<\/ul>\n
          \n
          When to Use Both Cores<\/h2>\n
          Use both cores when you have two genuinely independent tasks where one has hard real-time requirements and the other has high average CPU load. Stick with just the M7 when your application is straightforward and FreeRTOS task switching is sufficient.<\/p>\n
          \n
          Summary<\/h2>\n<\/p>\n
            \n
          • \nSTM32H745 uses AMP \u2014 each core runs independent firmware\n<\/li>\n
          • \nM7 is the boot master \u2014 it releases the M4 after initialisation\n<\/li>\n
          • \nPeripherals are assigned to cores in STM32CubeMX\n<\/li>\n
          • \nHSEM provides atomic inter-core synchronisation\n<\/li>\n
          • \nBest use: real-time control on M4, connectivity and display on M7 <\/li>\n<\/ul>\n\n\n
            <\/p>\n","protected":false},"excerpt":{"rendered":"
            A complete practical guide to setting up and running both cores of the STM32H745 simultaneously. Covers AMP architecture, CubeIDE project setup, HSEM inter-core communication, and real-world use cases for the NVX-H7 Pro and NVX-H7 Compact boards.<\/p>","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_post_was_ever_published":false},"categories":[1,62],"tags":[],"class_list":["post-1301","post","type-post","status-publish","format-standard","hentry","category-stm32h7","category-tutorials-guides"],"blocksy_meta":[],"yoast_head":"\nSTM32H745 Dual-Core Guide: M7 + M4 Running Simultaneously<\/title>\n<meta name=\"description\" content=\"Learn how the STM32H745 runs Cortex-M7 and Cortex-M4 cores simultaneously, with a practical guide to dual-core firmware.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.nvixeon.com\/fr\/stm32h745-dual-core-guide-running-cortex-m7-and-cortex-m4-simultaneously\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"STM32H745 Dual-Core: Running M7 and M4 Simultaneously\" \/>\n<meta property=\"og:description\" content=\"Complete guide to STM32H745 AMP dual-core architecture. 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