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The STM32N6 is a different kind of microcontroller. It is not just another Cortex-M upgrade — it is the first STM32 with a dedicated hardware Neural Processing Unit, and that changes what is possible on a microcontroller without a GPU, without an OS, and without Linux.
This article explains what the NPU actually is, how it compares to running inference on a standard Cortex-M7, and what that means for real AI edge projects.
What the STM32N6 Actually Contains
The main processor is an Arm Cortex-M55 running at up to 800MHz. The M55 is Arm’s most capable Cortex-M core — it includes the Helium MVE vector extension for DSP and ML workloads, running SIMD operations on integer and floating-point data. Compared to a Cortex-M7, the M55 with Helium can perform 4 to 8 times more multiply-accumulate operations per clock cycle on the right workload.
On top of the M55, the STM32N6 includes a hardware NPU — a fixed-function neural network accelerator. It is designed to run quantised neural network inference at INT4 and INT8 with minimal CPU involvement. The NPU delivers up to 600 GOPS at INT8, meaning it can process billions of multiply-accumulate operations per second without touching the Cortex-M55 at all.
This is the critical distinction. The NPU runs inference while the M55 handles everything else — sensor fusion, communication, display, control logic. You can run a real-time object detection model and still have full CPU headroom for your application.
How the NPU Compares to Cortex-M7
Consider running MobileNetV2 image classification at 224 by 224 input on three platforms. On an STM32H7 with M7 at 480MHz, inference takes around 180ms and the CPU is fully occupied. On the STM32N6 M55 at 800MHz without the NPU, it takes around 45ms but still fully occupies the CPU. On the STM32N6 with the NPU, the same inference takes around 8ms and the M55 is at approximately 5 percent load during the entire inference. That 8ms result with 5 percent CPU load means you can run MobileNetV2 at over 100 frames per second while simultaneously handling UART, a display refresh, sensor polling, and Ethernet — all on a single microcontroller with no operating system required.
What AI Models Run on the STM32N6 NPU
The NPU runs models quantised to INT8 or INT4 precision using STM32Cube.AI. Any model expressible as a standard neural network graph and quantised can be deployed. Confirmed working models include MobileNetV1, MobileNetV2, EfficientNet-Lite, and SqueezeNet for image classification; YOLOv5n, YOLOv8n, and SSD-MobileNet for object detection; UltraFace and RetinaFace small variant for face detection; DS-CNN and MobileNet audio for keyword spotting; and autoencoder architectures for anomaly detection.
The Deployment Pipeline
The deployment flow for the STM32N6 NPU is: train in PyTorch or TensorFlow in FP32, export to ONNX or TFLite, quantise to INT8 using post-training quantisation with a calibration dataset, import into STM32Cube.AI which analyses the model and shows predicted inference time on the NPU, generate C code targeting the NPU automatically, then integrate into your STM32 project and call ai_run() with your input tensor.
Memory Architecture
The STM32N6 has 4.2MB of contiguous internal SRAM, sufficient for activations of most small to medium models. Unlike earlier STM32 families, the N6 is flashless — it has no internal flash memory at all, so firmware and model weights are stored in external flash and loaded at runtime rather than baked into on-chip flash. It supports up to 512MB of external OctoSPI/XSPI flash for this purpose, plus optional LPDDR4 via XSPI on the NVX-N6 Vision Pro variant for larger models that exceed internal SRAM. A YOLOv8n model quantised to INT8 occupies approximately 3.2MB and requires around 1.5MB of SRAM for activations — the SRAM footprint fits comfortably within the NVX-N6 Vision’s internal memory, with weights streamed in from external flash.
Camera and Display Integration
The NVX-N6 Vision board exposes DCMI parallel camera for OV7670, OV2640, and similar sensors; MIPI-CSI2 for IMX219 and IMX477 class sensors; and MIPI-DSI display output for full HD video refresh with the ChromART hardware accelerator. A typical pipeline is: camera frame captured via DCMI, pre-processed by M55, inference on NPU, results overlaid on display via ChromART, display refreshed via MIPI-DSI — all in under 40ms total latency.
Who Should Use the STM32N6
The STM32N6 is the right choice when you need to run a neural network and do something useful with the result in real time, when you cannot use a Raspberry Pi because you need deterministic real-time behaviour, when a GPU is ruled out by power, cost, or form factor, and when your application needs battery operation or a harsh environment. It is not the right choice when your model is very large, when you need Linux, or when your application has no AI component — in that case the STM32H745 is more cost-effective.
The NVX-N6 Vision board is our STM32N6 development platform. It ships with a pinout diagram, full schematic, and an STM32Cube.AI deployment guide. View it at nvixeon.com/products or email info@nvixeon.com with any deployment questions.
